The "H" bridge inverter and the centre tapped inverter are the two basic circuits for controlled power flow between DC and AC circuits. Alternative DC-AC connections such as the PHASE-CONTROLLED RECTIFIER exist but cannot arbitrarily control the power flow and generally require a strong AC supply with which to connect.
Fig. 1: Half Bridge Inverter
2.1 Circuit Operation
When transistor T1 is ON, a voltage Vs/2 will be applied to the load. If the load draws positive current iL it will flow through T1 and supply energy to the load. IF the load current iL is negative it will flow back through D1 and Return energy to the DC source.
Similarly, if T2 is ON -Vs/2 will be applied to the load. If iL is positive it must flow through D2 returning energy to the DC source. If the current is negative it must flow through T2 supplying energy to the load.
2.2 Voltage levels
With T1 ON and drawing positive load current iL the load voltage will be less than Vs/2 by the ON-STATE voltage drop of T1. When the load current reverses, the load voltage will be higher than Vs/2 by the voltage drop across D1.
Fig. 2: Conduction Pattern for inverter
Normally the ON-STATE voltage and diode drops are ignored and the centre tapped inverter is represented as generating the voltage + Vs/2 or - Vs/2.
Fig. 3: "H" Bridge Inverter
3.1 Circuit Operations
With 4 switches there are 6 combinations to be examined.
T1-T2 ON or T3-T4 ON
Both create short circuits across the DC source and are invalid.
T1-T4 ON
Applies Vs to the load. With iL positive current passes through T1-T4, for iL negative the current is through D1-D4.
T2-T3 ON
Applies - Vs across the load. With iL positive the current flows through D2-D3 and returns energy to the DC source. With iL negative the current flows through T2-T3 and draws energy from the supply.
T1-T3 ON
Applies 0 volts across the load. For iL positive the path is T1-T3 for iL negative the path is D1-T3.
T2-T4 ON
Applies 0 volts across the load. For iL positive the path is through D2-T4. For iL negative the path is T2-D4.
3.2 Voltages
The "H" bridge can produce + Vs, 0 - VL across the load. Variations from this figure are caused by voltage drops across transistors and diodes. Corrections for this factor are discussed in IMPERFECTIONS.
We have seen that having T1 and T2 ON at the same time creates a supply short and is an invalid state. Similarly, T1 and T2 both OFF create an uncertain state where the load voltage will vary depending on the sign of the current. Logically the uncertain state can be avoided by having T2 ON when T1 is OFF and vice-versa, or. However, it takes a finite time per T1 to cease conduction from when the transistor drive is set to OFF. If T2 is turned ON while T1 is turning OFF then there will be a transient where T1 and T2 are shorting the supply and creating high dissipation in the transistors. To account for the finite switching time, a gap must be created between turning T1 OFF and turning T2 ON. This gap is called DEAD TIME and should be set just larger than the largest expected turn-off time of the switches. In fig 4 the deadtimes are labeled A,B,C,D. A sample conduction is shown below for the Half-bridge Inverter.
Fig. 4: Conduction and Overlap in Half Bridge
Initially, the current is positive and the load voltage follows the T1 waveform. As soon as T1 turns off, the current is carried by D2 and T2 does not conduct. When the current reverses, the load voltage follows the inverse of the T2 waveform, T1 does not conduct and the current swaps between T2 and D1.
Consider the generation a 50% output duty cycle waveform by having T1 ON, 45% of the time T2 ON 45%, and thus a 10% deadtime. The load voltage can be "high" between 45% of the time and 55% of the time depending on the direction of load current. This uncertainty in output voltage caused by the necessitiy of alllowing for deadtime can be corrected as discussed in CORRECTING INVERTER IMPERFECTIONS.
5. Inverter Imperfections
The perfect pulse width modulation normally assumes: DC source voltage is constant Zero ON STATE voltage across DIODE or TRANSISTOR Instant switching (no deadtime) For many applications, deviation from these assumptions cause a change of only a few percent in the voltage waveform and are ignored. When operating at high switch frequency and low modulation ratio, a reversal of current can cause the load voltage to double. If the dead time is 10% of a cycle of switching then a current reversal causes a change of output voltage of 10% of DC bus voltage. If the voltage being synthesised is only 10% of bus voltage we can then get a 100% change in output voltage.
5.1 DC BUS RIPPLE
One connection for an inverter is with a rectifier supplying the DC bus.
Fig. 5: Simple Rectifier Inverter
The inductor L can help smooth the current flow to the DC bus but typically there will be significant variation in current at twice the main's frequency. The energy supply to the load will cause another variation of current at twice load frequency. (For 3 phase balanced loads ripple in each phase balances the others giving none of this load ripple term).
In addition there will be switch frequency currents to and from the DC bus capacitor. Because of the finite impedance of the capacitor the DC bus voltage will not be constant. There is no easy method to correct for switch frequency variations in DC bus voltage but slower variations can be corrected with the modulation.
Output voltage = Modulation pattern * DC bus voltage.
Clearly the output voltage can be corrected for a 5% increase of DC bus voltage by a 5% decrease of the ON times of the modulation pattern. Thus, if generating a sin(wt) by sine-sawtooth modulation. A 5 % increase of bus voltage can be compensated by using
in the PWM comparison.
5.2 ON-STATE VOLTAGE DROP
If we represent the ON-STATE drop of transistors as a constant T and of a DIODE as D then when a phase leg has a duty ratio of "d" the voltage averaged over the switch cycle is:
Thus instead of comparing Vph with Vs to find duty ratio "d", use:
If
this modulation can be implemented by comparing
5.3 DEAD-TIME CORRECTION
Fig. 6: Waveforms for correction of deadtime.
Normally PWM is generated by sampling the required signal at the corners of the sawtooth wave giving samples s1 and s2. From these samples the desired output voltage should go low at 'a' and high at 'b'. If the current is positive the output voltage follows the edges of T1. When the output current is negative the output voltage follows the edges of T2 which are adjusted as shown to match the PWM intersections again at 'a' and 'b'. To implement the deadtime 'd' when both switches are OFF the additional edges at 'c' and 'e' must be generated. One means of implementing a dead-time is to generate a nominal signal Tn from which T1 and T2 are formed. For this scheme, T1 follows Tn but any turn-on is delayed by 'd'. T2 follows the inverse of Tn but any turn-on is delayed by 'd'. The desired Tn for both directions of current is illustrated in the diagram and is generated by
POSITIVE EDGE OF SAWTOOTH
compare sawtooth with Vph for i>0
compare sawtooth with Vph- for i<0
NEGATIVE EDGE OF SAWTOOTH
compare sawtooth with Vph+ for i>0
compare sawtooth with Vph for i<0
The sawtooth is usually between voltages corresponding to DC bus voltage Vs and for a desired deadtime 'd' the value of the offset is
Including this correction to regular sampled PWM will give exact correction to deadtime error provided the current is continuous. For natural sampled PWM, the correction will not be exact but differences will be less than the difference between natural and regular PWM.
Copyright © G. Ledwich 1998.
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